1. Field of the Invention
The present invention relates to an integrated circuit and method for frequency synthesis and clock generation. More specifically, the present invention relates to a programmable, and preferably, self-resetting Johnson counter incorporated within a dynamic feedback loop for frequency synthesis of an internal clock.
2. Background of the Field
It is common knowledge that a microprocessor internally operates at a clock frequency substantially greater than a clocking frequency of a system clock external to the microprocessor ("the external system clock"). In fact, in recent years, microprocessor internal clock frequencies have increased disproportionately with respect to external system clock frequencies. As a result, it has become necessary to employ frequency synthesis in order to generate the microprocessor clock as a function of the external system clock. A paramount reason for such frequency synthesis is to enable the microprocessor to perform at its fastest possible frequency while data exchange between the microprocessor and an external board system can proceed at a rate limited by system constraints, such as, signal flight time across board traces, heavy board capacitances and the like.
In order to accomplish frequency synthesis, dynamic feedback loops have been employed within the microprocessor ("MP") 1 as shown in FIG. 1. An example of the dynamic feedback loop includes, but are not limited to, a phase-locked-loop ("PLL"). The PLL 2 is a feedback component including an internal oscillator 3 generating a first frequency which is usually substantially greater than a frequency of a external system clock 10 inputted into the PLL 2. The internal oscillator 3 outputs an oscillator signal having the first frequency through a PLL output signal line 4, which couples a first and second dividers 5 and 6 to the PLL 2. As a result, clock signals within the MP 1, namely an internal microprocessor clock signal ("MP.sub.-- CLK signal") 7 and an internal I/O clock signal ("I/O.sub.-- CLK signal") 8, are obtained by inputting the oscillator signal into the first and second dividers 5 and 6 respectively. The I/O.sub.-- CLK signal 8 is synchronized to the external system clock 10 and is fed back into the PLL 2 via a feedback signal line 9 in order to eliminate skew between the external system clock and the I/O.sub.-- CLK signal 8. Moreover, in order to eliminate skew between the MP.sub.-- CLK signal 7 and the I/O.sub.-- CLK signal 8, the delay through the first and second dividers 5 and 6 must be equal, even though such dividers may be programmed differently.
Although there exist many different types of dividers (e.g., counters) in the marketplace, most of them have extremely slow critical paths and/or are not programmable, preventing easy modification of the dividers to support different system requirements. Circuit designers have commonly used Johnson counters to perform synchronous high frequency synthesis and high speed clock generation. Nevertheless, there does not exist any known method for resetting two Johnson counters to support frequency synthesis. Moreover, in today's technology, there does not exist a suitable method for implementing a Johnson counter in an integrated circuit processed with CMOS technology due to very high frequency demands, often much higher than that of normal logic circuits on the microprocessor.